The present invention relates generally to a memory device and, more particularly, to a semiconductor memory device and a method of fabricating the same.
Gate coupling ratio (GCR) is one of the important features of flash memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory. A flash memory device with a higher GCR may exhibit a lower operating voltage and operate at a faster device speed.
FIG. 1A is a cross-sectional diagram illustrating a memory cell 1 having a single poly-silicon gate structure in prior art. Referring to FIG. 1A, the memory cell 1 includes a p-type substrate 10, an n-well 11, a transistor 14, an isolator 12 and a control terminal 19. A gate conductor 17 of the transistor 14 and a conductor 18 over the n-well 11, which are electrically coupled to each other (not shown) and formed in a single layer, constitute the single poly-silicon gate structure. The GCR may represent a voltage in the conductors 17 and 18 induced by an external voltage applied to the control terminal 19, and may be expressed as a function of relevant capacitances of the memory cell 1 in Equation (1) below.
                              G          ⁢                                          ⁢          C          ⁢                                          ⁢          R                =                              C            1                                              C              1                        +                          C              2                                                          Equation        ⁢                                  ⁢                  (          1          )                    
where C1 represents the capacitance defined by the gate layer 17, a dielectric layer 15 and the n-well 11, and C2 represents the capacitance defined by the gate layer 18, a dielectric layer 16 and the substrate 10. FIG. 2 is a diagram shows an equivalent circuit of the capacitors C1 and C2, which are connected in series.
To obtain a relatively high GCR, an additional capacitor in parallel with the capacitor C1 may be added, thereby increasing the total capacitance each in the numerator and denominator of Equation (1). Accordingly, it may be desirable to have a semiconductor memory device that has a relatively high GCR to reduce the operating voltage and enhance the device speed. It may also be desirable to have a method of manufacturing a semiconductor memory device having a relatively high GCR without increasing the size of the memory device.